HBM is the tightest bottleneck in the AI cycle — and three companies own it

The AI-compute story most retail traders absorb is a GPU story. $NVDA announces a new accelerator, the price moves, the tape decides the AI cycle is or isn't accelerating. The story is half-right and half-misleading.

A modern AI accelerator is not a GPU die. It's a GPU die sitting on an interposer next to four-to-twelve stacks of High-Bandwidth Memory (HBM), with a Taiwan Semiconductor packaging step (CoWoS) wiring them together. The GPU die is where the math happens. The HBM is what feeds the math. If the memory bandwidth isn't there, the GPU stalls — the math waits, the watts burn, the cluster runs slower than spec.

For the last three generations, HBM bandwidth has been the gating spec, not GPU flops. Each new GPU generation ships with more HBM stacks per die than the one before. The H100 had five stacks of HBM3. The B100 ships with eight stacks of HBM3E. The next-gen Rubin family is being designed around HBM4, with stack counts likely higher again.

Three companies make this memory at scale. Together they hold essentially 100% of the HBM market. This is what they ship, what's actually trade-able, and why one of them is structurally hard to buy from a US-retail account.

What HBM actually is (the 2-minute version)

Standard DRAM modules (DDR5 in a server, GDDR6/7 on a consumer GPU) are wide-and-flat — chips sit on a PCB, talk to the processor over a parallel bus with a finite pin count. Bandwidth scales with bus width, and bus width is physically constrained.

HBM solves the bandwidth problem by going vertical. The chips are stacked — 8-high or 12-high — connected to each other through Through-Silicon Vias (TSVs, microscopic copper holes etched right through the die). The whole stack sits on a silicon interposer next to the processor, not across the board. The bus width is huge — HBM3E runs roughly 1 TB/s per stack. With eight stacks per GPU, you're feeding the math at ~8 TB/s, which is what a B100 needs to keep its tensor cores from idling.

Two consequences of the stacked architecture matter for the supply chain:

1. Yield is the gating factor. Stacking eight dice perfectly aligned with thousands of TSVs each is hard. Yield per stack is meaningfully lower than yield per discrete chip. Capacity is set by good stacks shipped, not chips fabbed.
2. Packaging is the second bottleneck. The interposer that wires the HBM stacks to the GPU is fabricated by TSMC using their CoWoS process (Chip-on-Wafer-on-Substrate). CoWoS capacity has been the single tightest constraint on Nvidia volume since 2023. TSMC has been expanding aggressively — multiple new fabs dedicated to CoWoS — but the ramp lags demand.

This is why "HBM is the bottleneck" isn't loose talk. It's a structural claim about which physical resource determines how many AI accelerators ship per quarter.

The three companies

SK Hynix — the volume leader

SK Hynix shipped the first volume HBM3E to Nvidia in late 2024, beating Samsung to qualification by roughly six months. That gap matters: HBM contracts run on long-cycle volume commitments, and Nvidia locked in SK Hynix as the primary HBM3E supplier for the Blackwell ramp. As of the most recent reporting cycle, SK Hynix holds approximately half the global HBM market by revenue and the majority of HBM3E specifically.

Primary listing: Korea Exchange, ticker 000660.KS. There is no clean US ADR. A US-retail trader who wants direct SK Hynix exposure either needs a broker with KRX access (a short list — see below) or settles for indirect exposure via Korea-ETFs (EWY, FLKR), which dilutes the thesis.

Samsung Electronics — the recovering giant

Samsung is the larger company by revenue overall, but they came late to HBM3E. Multiple public reports describe a Nvidia qualification process that took longer than Samsung's internal targets — the implication being that yield + thermal performance on Samsung's HBM3E stacks needed additional iterations. By 2025 Samsung was shipping qualified HBM3E in volume, but the early-mover share advantage had already locked in for SK Hynix.

Samsung is a much broader business than memory — phones, displays, foundry services, consumer appliances. Buying the parent company gets you HBM exposure diluted across the rest of the conglomerate. For a pure memory-bottleneck play, the dilution argues for going to SK Hynix directly when possible, or pairing the Samsung exposure with hedges.

Primary listing: Korea Exchange, ticker 005930.KS. London-listed GDRs exist (SMSN.LN) with thin liquidity; US pink-sheet variants exist but are tax-messy. No clean US ADR for retail.

Micron — the US-listed pure-play

$MU is the third player. Smaller HBM share than either Korean competitor but growing. Their HBM3E started shipping to Nvidia in 2024. The 2026 capex plan publicly described includes HBM-dedicated capacity expansion in both Taiwan and Japan.

The structural advantage for US-retail: Micron lists on Nasdaq. You can buy it from any broker. Options chain is liquid. 13F filings show institutional accumulation — see the Q1 2026 13F tape for which funds have been adding.

The structural disadvantage: Micron's HBM is part of a broader memory business that also makes commodity DDR + NAND. Commodity DRAM cycles are vicious (the 2022-2023 trough cut earnings to near-zero); Micron's stock moves with the overall DRAM cycle even on quarters when HBM is shipping well.

What's actually trade-able

| Name | Primary listing | Clean US access? | HBM share | Pure-play? | |---|---|---|---|---| | SK Hynix | KRX 000660 | No clean ADR | ~50%+ | Mostly (60-70% memory) | | Samsung Electronics | KRX 005930 | No clean ADR | ~30% | No (memory ~30% of group) | | Micron ($MU) | Nasdaq | Yes | ~10%, growing | Mostly (memory pure) | | TSMC ($TSM) | TWSE 2330 (ADR clean) | Yes via ADR | N/A — packaging | Foundry exposure |

The shape of the basket depends on your access. Three cases:

• US-only retail account. Your HBM exposure is $MU + $TSM. You're missing the two largest players outright. The basket is significantly under-weighted on the trade.
• Direct global access. Add SK Hynix + Samsung primaries. The basket now spans ~100% of HBM supply, and you can size by company-specific share.
• Want to express more granular views. Options exist on $MU directly. No US-listed options on Samsung / SK Hynix. If you want to hedge memory exposure with puts during a perceived cycle peak, the US-only basket can't do it; the global basket can.

We map this access constraint in detail in a separate article on global broker reach.

What the QA platform shows

The HBM names cluster tightly in the memory bubble of our taxonomy. Pairwise residualized correlation between $MU, SK Hynix, and Samsung's memory-business proxy runs above 0.70 on the 252-day window — well above the SPY-residualized noise floor. They trade as a bloc. Methodology: residualized correlation.

What this means tactically: when the HBM thesis takes a step forward (a fresh Nvidia volume guide-up, a new HBM4 spec disclosure, a CoWoS expansion announcement), the bloc moves together — and when it takes a step back (a memory-cycle softness print, a Korean political shock, a foundry capex revision), the bloc draws down together. Position-sizing across the bloc as a basket reduces idiosyncratic risk; position-stacking inside the bloc multiplies it.

The honest tradeoffs

This is the bottleneck right now. It does not mean the trade has no risk:

• Memory is cyclical. The HBM cycle is currently inflecting up, but the broader DRAM cycle has always turned. Micron's earnings in 2022-2023 were near zero. The HBM mix shift insulates somewhat — HBM is a higher-margin product than commodity DDR — but it doesn't immunize against an overall demand softening.
• Korean political risk is non-trivial. Samsung and SK Hynix are subject to Korean export-control coordination with US policy on China. A meaningful chunk of HBM end-demand has historically routed to China-based hyperscalers; restrictions there shift the picture.
• CoWoS capacity could un-bottleneck. TSMC's expansion plan is aggressive. If the foundry catches up faster than expected, the constraint shifts from HBM yield (Korean) to HBM volume (capacity bottleneck eases), which compresses the pricing premium. Watch TSMC's quarterly capex commentary for inflection signals.
• Custom silicon could displace some HBM demand long-term. Hyperscalers building their own accelerators (Trainium, TPU, MTIA) use HBM today but specify it themselves; if they push to alternative on-package memory architectures, HBM unit demand could grow slower than the cluster count. Multi-year horizon, not 2026 risk.

How to actually act on this

If the structural argument lands and you want exposure:

1. Decide your access level first. US-only retail = $MU + $TSM only. Global access = add the Korean primaries. The basket completeness depends on this single decision.
2. For direct access to Samsung + SK Hynix primaries, open an Interactive Brokers account — that's the broker we use for the Korea + Taiwan legs of the supply-chain basket. Full reasoning + tradeoffs on our broker page.
3. For US-only exposure, $MU + $TSM on any broker; pair with $NVDA / $AVGO for the compute-demand side.
4. Watch the right catalysts — TSMC quarterly capex commentary, SK Hynix HBM3E + HBM4 volume guides, the Korean memory price index, and any Nvidia commentary on HBM availability in their quarterly calls. The HBM cycle's inflection points are signaled there before they hit the index.

The compute side of the AI trade is crowded. The memory side that determines whether the compute even works is concentrated in three companies and one packaging house. That's where the structural lock-in lives.